Read channel integrated circuits may include significant digital signal processing after an analog signal has been received. A post-processor module is generally utilized to improve a bit error rate (BER) performance of the read channel over what a Viterbi detector may be capable of solely. A post-processor module receives a data stream from the Viterbi detector and makes corrections to the data based on additional information provided by coding redundancy, error event matched filter metrics, or additional Viterbi detector data.
Post-processors known to the art utilize matched filters to generate error event data and metrics for each row. A list of most probable error events with even and odd parity are maintained for each row. A row process is performed to enforce row parity and a column process is performed in an attempt to enforce all column parity. A column correction process is utilized to alter the data received from the Viterbi detector in order to remove errors. The column correction process includes determing a column parity check syndrome and checking all even parity error events from the list for the one which matches the syndrome the most. However, the column correction process known to the art miscorrects data too frequently. The miscorrection of data leads to a BER which is higher than desired and adversely affects the performance of the error correction code. Consequently, an improved method and system for reducing miscorrections of data in a post-processor is necessary.